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ltc6912 1 6912fa features typical applicatio u 2 channels with independent gain control ltc6912-1: (0, 1, 2, 5, 10, 20, 50, and 100v/v) ltc6912-2: (0, 1, 2, 4, 8, 16, 32, and 64v/v) offset voltage = 2mv max (?0 c to 85 c) channel-to-channel gain matching of 0.1db max 3-wire spi tm interface extended gain-bandwidth at high gains wired-or outputs possible (2:1 analog mux function) low power hardware shutdown (gn-16 only, 2 a max at 2.7v) rail-to-rail input range rail-to-rail output swing single or dual supply: 2.7v to 10.5v total input noise: 12.6nv/ hz total system dynamic range to 115db 16-pin gn (ssop) or 12-pin dfn package options data acquisition systems dynamic gain changing automatic ranging circuits automatic gain control dual programmable gain amplifiers with serial digital interface the ltc ? 6912 is a family of dual channel, low noise, digitally programmable gain amplifiers (pga) that are easy to use and occupy very little pc board space. the gains for both channels are independently programmable using a 3-wire spi interface to select voltage gains of 0, 1, 2, 5, 10, 20, 50, and 100v/v (ltc6912-1 ); and 0, 1, 2, 4, 8, 16, 32, and 64v/v (ltc6912-2). all gains are inverting. the ltc6912 family consists of 2 matched amplifiers with rail-to-rail outputs. when operated with unity gain, they will also process rail-to-rail input signals. a half-supply reference generated internally at the agnd pin supports single power supply applications. operating from single or split supplies from 2.7v to 10.5v total, the ltc6912-x family is offered in tiny ssop and dfn-12 packages. , ltc and lt are registered trademarks of linear technology corporation. ina agnd inb 1 f 0.1 f v ina v inb v outa = gain a ? v ina v outb = gain b ? v inb out a out b ltc6912-x v + 3v v C shdn cs/ld data clk shdn cs/ld d in 5 6 7 8 10 9 dgnd d out 2 12 14 3 4 15 13 chb cha 3-wire spi interface 6912 ta01a frequency (khz) 0.1 gain (db) 40 30 20 10 0 C10 1 10 100 1000 6912 ta01b 10000 gain of 64 gain of 32 gain of 16 gain of 8 gain of 4 gain of 2 gain of 1 v s = 2.5v v in = 10mv rms ltc6912-2 frequency response a dual, matched low noise pga (16-lead ssop package) descriptio u all other trademarks are the property of their respective owners. applicatio s u
ltc6912 2 6912fa total supply voltage (v + to v C ) ............................... 11v input current ...................................................... 10ma operating temperature range (note 2) ltc6912c-1, ltc6912c-2 ..................C40 c to 85 c ltc6912i-1, ltc6912i-2 .....................C40 c to 85 c ltc6912h-1, ltc6912h-2 (gn-16 only) .....................................C40 c to 125 c order part number dfn part* marking 69121 69121 69122 69122 ltc6912cde-1 ltc6912ide-1 ltc6912cde-2 ltc6912ide-2 absolute axi u rati gs w ww u package/order i for atio uu w (note 1) consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. specified temperature range (note 3) ltc6912c-1, ltc6912c-2 ..................C40 c to 85 c ltc6912i-1, ltc6912i-2 .....................C40 c to 85 c ltc6912h-1, ltc6912h-2 (gn-16 only) .....................................C40 c to 125 c storage temperature range ..................C65 c to 150 c ue package ....................................... C65 c to 125 c lead temperature (soldering, 10sec)................... 300 c order part number gn part marking 69121 6912i1 6912h1 69122 6912i2 6912h2 ltc6912cgn-1 ltc6912ign-1 ltc6912hgn-1 ltc6912cgn-2 ltc6912ign-2 ltc6912hgn-2 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ t jmax = 125 c, ja = 160 c/w 12 11 10 9 8 7 1 2 3 4 5 6 outa v C outb v + dgnd dout ina agnd inb cs/ld din clk top view ue12 package 12-lead (4mm 3mm) plastic dfn exposed pad is connected to v C (pin 13), must be soldered to pcb 13 top view gn package 16-lead narrow plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 nc ina agnd inb shdn cs/ld d in clk nc out a v C out b v + nc dgnd d out t jmax = 150 c, ja = 120 c/w
ltc6912 3 6912fa u u u gai setti gs a d properties table 1. ltc6912-1 gain settings and properties upper/lower nominal nibble voltage gain maximum linear input range (v p-p ) q7 q6 q5 q4 dual 5v single 5v single 3v nominal input nominal output q3 q2 q1 q0 volts/volt db supply supply supply impedance (k ? ) impedance ( ? ) 0000 0 C120 10 5 3 (open) 0.4 0001 C1 0 10 5 3 10 0.7 0010 C2 6 5 2.5 1.5 5 3.4 0011 C5 14 2 1 0.6 2 3.4 0100 C10 20 1 0.5 0.3 1 3.4 0101 C20 26 0.5 0.25 0.15 1 6.4 0110 C50 34 0.2 0.1 0.06 1 15 0111 C100 40 0.1 0.05 0.03 1 30 1 0 x x 0 C120 10 5 3 (open) (open) 1 1 x x not used (note 11) not used table 2. ltc6912-2 gain settings and properties upper/lower nominal nibble voltage gain maximum linear input range (v p-p ) q7 q6 q5 q4 dual 5v single 5v single 3v nominal input nominal output q3 q2 q1 q0 volts/volt db supply supply supply impedance (k ? ) impedance ( ? ) 0000 0 C120 10 5 3 (open) 0.4 0001 C1 0 10 5 3 10 0.7 0010 C2 6 5 2.5 1.5 5 3.4 0011 C4 12 2.5 1.25 0.75 2.5 3.4 0100 C8 18.1 1.25 0.625 0.375 1.25 3.4 0101 C16 24.1 0.625 0.3125 0.188 1.25 6.4 0110 C32 30.1 0.3125 0.156 0.094 1.25 15 0111 C64 36.1 0.156 0.078 0.047 1.25 30 1 0 x x 0 C120 10 5 3 (open) (open) 1 1 x x not used (note 11) not used
ltc6912 4 6912fa electrical characteristics the denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1, r l = 10k to midsupply point, unless otherwise noted. c, i grades h grade parameter conditions min typ max min typ max units specifications for both the ltc6912-1 and the ltc6912-2 total supply voltage (v s ) 2.7 10.5 2.7 10.5 v supply current per channel both amplifiers active (gain = 1) v s = 2.7v, v ina = v inb = v agnd 1.75 2.75 1.75 3.0 ma v s = 5v, v ina = v inb = v agnd 2.0 3.0 2.0 3.25 ma v s = 5v, v ina = v inb = 0v 2.25 3.5 2.25 3.75 ma supply current per channel both amplifiers inactive (state 1000) (software shutdown) v s = 2.7v, v ina = v inb = v agnd 150 255 150 280 a v s = 5v, v ina = v inb = v agnd 200 325 200 350 a v s = 5v, v ina = v inb = 0v 265 750 265 750 a total-supply current v s = 2.7v, v shdn = 2.43v 0.3 2 0.3 5 a (hardware shutdown, v s = 5v, v shdn = 4.5v 3.6 10 3.6 10 a gn-16 package only) v s = 5v, v shdn = 4.5v 20 50 20 50 a output voltage swing low v s = 2.7v, r l = 10k tied to midsupply point 12 30 12 35 mv (note 4) v s = 2.7v, r l = 500 ? tied to midsupply point 60 110 50 125 mv v s = 5v, r l = 10k tied to midsupply point 20 40 20 45 mv v s = 5v, r l = 500 ? tied to midsupply point 100 170 90 190 mv v s = 5v, r l = 10k tied to 0v 30 50 30 60 mv v s = 5v, r l = 500 ? tied to 0v 190 260 80 290 mv output voltage swing high v s = 2.7v, r l = 10k tied to midsupply point 10 20 10 25 mv (note 4) v s = 2.7v, r l = 500 ? tied to midsupply point 50 80 50 90 mv v s = 5v, r l = 10k tied to midsupply point 15 30 15 35 mv v s = 5v, r l = 500 ? tied to midsupply point 90 160 80 175 mv v s = 5v, r l = 10k tied to 0v 20 40 20 45 mv v s = 5v, r l = 500 ? tied to 0v 180 250 180 270 mv output short-circuit current v s = 2.7v 27 27 ma (note 5) v s = 5v 35 35 ma agnd open-circuit voltage v s = single 5v supply, v shdn = 0.5v 2.45 2.5 2.55 2.45 2.5 2.55 v (gn-16 package only) v s = single 5v supply, v shdn = 4.5v 2.65 2.65 v agnd (common mode) v s = single 2.7v supply 0.55 1.6 0.55 1.6 v input voltage range v s = single 5v supply 0.75 3.65 0.75 3.65 v v s = 5v C4.3 3.2 C4.3 3.2 v agnd rejection (i.e., common v s = 2.7v, v agnd = 1.1v to 1.6v 55 80 50 80 db mode rejection or cmrr) v s = 5v, v agnd = C2.5v to 2.5v 55 75 50 75 db power supply rejection ratio (psrr) v s =2.7v to 5v 60 80 57 80 db slew rate gain = 1 v s = 5v, v outa = v outb = 1.1v to 3.9v 12 12 v/ s v s = 5v, v outa = v outb = 1.4v 16 16 v/ s gain = 10 (C1), gain = 8 (C2) v s = 5v, v outa = v outb = 1.1v to 3.9v 20 20 v/ s v s = 5v, v outa = v outb = 1.4v 26 26 v/ s signal attenuation at gain = 0 setting gain = 0 (digital inputs 0000), C120 C120 db f = 200khz signal attenuation in software (state = 1000) C120 C120 db shutdown
ltc6912 5 6912fa the denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1, r l = 10k to midsupply point, unless otherwise noted. electrical characteristics c, i grades h grade parameter conditions min typ max min typ max units specifications for both the ltc6912-1 and the ltc6912-2 shdn input high voltage v s = single 2.7v 2.43 2.43 v (gn-16 package only) v s = single 5v 4.5 4.5 v v s = 5v 4.5 4.5 v shdn input low voltage v s = single 2.7v 0.27 0.27 v (gn-16 package only) v s = single 5v 0.5 0.5 v v s = 5v 0.5 0.5 v shdn pin 5, input high current v s = single 2.7v 0.2 0.2 a (gn-16 package only) v s = single 5v 1 1 a v s = 5v 1 1 a shdn pin 5, input low current v s = single 2.7v 0.2 0.2 a (gn-16 package only) v s = single 5v 1 1 a v s = 5v 1 1 a specifications for the ltc6912-1 only voltage gain (note 6) v s = 2.7v, gain = 1, r l = 10k C0.07 0 0.07 C0.08 0 0.07 db v s = 2.7v, gain = 1, r l = 500 ? C0.11 C0.02 0.07 C0.13 C0.02 0.07 db v s = 2.7v, gain = 2, r l = 10k 5.94 6.01 6.08 5.93 6.01 6.08 db v s = 2.7v, gain = 5, r l = 10k 13.85 13.95 14.05 13.8 13.95 14.05 db v s = 2.7v, gain = 10, r l =10k 19.7 19.93 20.1 19.65 19.93 20.1 db v s = 2.7v, gain = 10, r l = 500 ? 19.55 19.85 20.05 19.35 19.85 20.05 db v s = 2.7v, gain = 20, r l = 10k 25.75 25.94 26.1 25.65 25.94 26.1 db v s = 2.7v, gain = 50, r l = 10k 33.5 33.8 34.05 33.40 33.8 34.05 db v s = 2.7v, gain = 100, r l = 10k 39.2 39.6 40.0 39.0 39.6 40.0 db v s = 2.7v, gain = 100, r l = 500 ? 37.3 38.9 39.7 36.20 38.9 39.7 db v s = 5v, gain = 1, r l = 10k C0.08 0.01 0.08 C0.09 0.01 0.08 db v s = 5v, gain = 1, r l = 500 ? C0.11 C0.01 0.07 C0.13 C0.01 0.07 db v s = 5v, gain = 2, r l = 10k 5.95 6.02 6.09 5.94 6.02 6.09 db v s = 5v, gain = 5, r l = 10k 13.8 13.96 14.1 13.78 13.96 14.1 db v s = 5v, gain = 10, r l = 10k 19.8 19.94 20.1 19.75 19.94 20.1 db v s = 5v, gain = 10, r l = 500 ? 19.6 19.87 20.1 19.45 19.87 20.1 db v s = 5v, gain = 20, r l = 10k 25.78 25.94 26.08 25.75 25.94 26.08 db v s = 5v, gain = 50, r l = 10k 33.5 33.84 34.1 33.4 33.84 34.1 db v s = 5v, gain = 100, r l = 10k 39.3 39.7 40.1 39.1 39.7 40.1 db v s = 5v, gain = 100, r l = 500 ? 37.75 39.2 39.85 36.6 39.2 39.85 db v s = 5v, gain = 1, r l = 10k C0.06 0.01 0.08 C0.07 0.01 0.08 db v s = 5v, gain = 1, r l = 500 ? C0.10 0 0.08 C0.11 0 0.08 db v s = 5v, gain = 2, r l = 10k 5.95 6.02 6.09 5.94 6.02 6.09 db v s = 5v, gain = 5, r l = 10k 13.8 13.96 14.1 13.79 13.96 14.1 db v s = 5v, gain = 10, r l = 10k 19.78 19.94 20.08 19.75 19.94 20.08 db v s = 5v, gain = 10, r l = 500 ? 19.68 19.91 20.05 19.58 19.91 20.05 db v s = 5v, gain = 20, r l = 10k 25.78 25.95 26.08 25.73 25.95 26.08 db v s = 5v, gain = 50, r l = 10k 33.65 33.87 34.05 33.60 33.87 34.05 db v s = 5v, gain = 100, r l = 10k 39.4 39.8 40.2 39.25 39.8 40.2 db v s = 5v, gain = 100, r l = 500 ? 38.6 39.5 39.9 37.6 39.5 39.9 db
ltc6912 6 6912fa c, i grades h grade parameter conditions min typ max min typ max units electrical characteristics the denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1, r l = 10k to midsupply point, unless otherwise noted. specifications for the ltc6912-1 only channel-to-channel v s = 2.7v, gain = 1, r l = 10k C0.1 0.02 0.1 C0.1 0.02 0.1 db voltage gain match v s = 2.7v, gain = 1, r l = 500 ? C0.1 0.02 0.1 C0.1 0.02 0.1 db (note 6) v s = 2.7v, gain = 2, r l = 10k C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 2.7v, gain = 5, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 2.7v, gain = 10, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 2.7v, gain = 10, r l = 500 ? C0.15 0.02 0.15 C0.2 0.02 0.2 db v s = 2.7v, gain = 20, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 2.7v, gain = 50, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 2.7v, gain = 100, r l = 10k C0.2 0.02 0.2 C0.2 0.02 0.2 db v s = 2.7v, gain = 100, r l = 500 ? C1.0 0.02 1.0 C1.5 0.02 1.5 db v s = 5v, gain = 1, r l = 10k C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 5v, gain = 1, r l = 500 ? C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 5v, gain = 2, r l = 10k C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 5v, gain = 5, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 10, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 10, r l = 500 ? C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 20, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 50, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 100, r l = 10k C0.2 0.02 0.2 C0.2 0.02 0.2 db v s = 5v, gain = 100, r l = 500 ? C0.8 0.02 0.8 C1.2 0.02 1.2 db v s = 5v, gain = 1, r l = 10k C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 5v, gain = 1, r l = 500 ? C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 5v, gain = 2, r l = 10k C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 5v, gain = 5, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 10, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 10, r l = 500 ? C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 20, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 50, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 100, r l = 10k C0.2 0.02 0.2 C0.2 0.02 0.2 db v s = 5v, gain = 100, r l = 500 ? C0.6 0.02 0.6 C0.9 0.02 0.9 db gain temperature coefficient v s = 5v, gain = 1, r l = open 2 2 ppm/ c (note 6) v s = 5v, gain = 2, r l = open C1.5 C1.5 ppm/ c v s = 5v, gain = 5, r l = open C11 C11 ppm/ c v s = 5v, gain = 10, r l = open C30 C30 ppm/ c v s = 5v, gain = 20, r l = open C40 C40 ppm/ c v s = 5v, gain = 50, r l = open C70 C70 ppm/ c v s = 5v, gain = 100, r l = open C140 C140 ppm/ c channel-to-channel gain v s = 5v, gain = 1, r l = open 1 1 ppm/ c temperature coefficient match v s = 5v, gain = 2, r l = open 1 1 ppm/ c (gain specified in dbs) v s = 5v, gain = 5, r l = open 0.2 0.2 ppm/ c (note 6) v s = 5v, gain = 10, r l = open C1 C1 ppm/ c v s = 5v, gain = 20, r l = open C1 C1 ppm/ c v s = 5v, gain = 50, r l = open C3 C3 ppm/ c v s = 5v, gain = 100, r l = open C3 C3 ppm/ c channel-to-channel isolation f = 200khz, (note 7) v s = 5v, gain = 1, r l = 10k 113 113 db v s = 5v, gain = 10, r l = 10k 108 108 db v s = 5v, gain = 100, r l = 10k 89 89 db
ltc6912 7 6912fa electrical characteristics the denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1, r l = 10k to midsupply point, unless otherwise noted. c, i suffixes h suffix parameter conditions min typ max min typ max units specifications for the ltc6912-1 only offset voltage magnitude gain = 1 0.125 2 0.125 3.5 mv (internal op-amp, note 8) offset voltage magnitude gain = 1 0.25 3.5 0.25 6.5 mv referred to ina or inb pins gain = 10 0.14 2 0.14 4 mv (note 8) input offset voltage drift, 6 10 v/ c internal op amp dc input resistance at dc v ina or v inb = 0v ina or inb pins (note 9) gain = 0 >10 >10 m ? state = 8, software shutdown >10 >10 m ? gain = 1 10 10 k ? gain = 2 55k ? gain = 5 22k ? gain > 5 11k ? dc input resistance drift at gain = 1 85 95 ppm/ c ina or inb pins (note 9) gain = 2 90 100 ppm/ c gain = 5 100 110 ppm/ c gain = 10 120 130 ppm/ c gain = 20 130 140 ppm/ c gain = 50 150 160 ppm/ c gain = 100 190 200 ppm/ c dc input resistance match gain = 1 10 10 ? r ina -r inb gain = 2 55 ? gain = 5 55 ? gain > 5 55 ? dc small signal output resistance dc v ina or v inb = 0v at out a or out b pins gain = 0 0.4 0.4 ? gain = 1 0.7 0.7 ? gain = 2 1.0 1.0 ? gain = 5 1.9 1.9 ? gain = 10 3.4 3.4 ? gain = 20 6.4 6.4 ? gain = 50 15 15 ? gain = 100 30 30 ? state = 8, software shutdown >1 >1 m ? gain bandwidth product gain = 100 18 33 50 16 33 50 mhz wideband noise f = 1khz to 200khz (referred to input) gain = 0 (output noise only) 8.9 8.9 v rms gain = 1 15.6 15.6 v rms gain = 2 11.1 11.1 v rms gain = 5 8.3 8.3 v rms gain = 10 7.4 7.4 v rms gain = 20 7.0 7.0 v rms gain = 50 6.7 6.7 v rms gain = 100 6.3 6.3 v rms
ltc6912 8 6912fa electrical characteristics the denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1, r l = 10k to midsupply point, unless otherwise noted. c, i grades h grade parameter conditions min typ max min typ max units specifications for the ltc6912-1 only voltage noise density f = 50khz (referred to input) gain = 1 35.6 35.6 nv/ hz gain = 2 24.8 24.8 nv/ hz gain = 5 19.1 19.1 nv/ hz gain = 10 16.7 16.7 nv/ hz gain = 20 16 16 nv/ hz gain = 50 15.4 15.4 nv/ hz gain = 100 15.1 15.1 nv/ hz total harmonic distortion gain = 10, f in = 10khz, v out = 1v rms C90 C90 db 0.003 0.003 % gain = 10, f in = 100khz, C82 C82 db v out = 1v rms 0.008 0.008 % specifications for the ltc6912-2 only voltage gain (note 6) v s = 2.7v, gain = 1, r l = 10k C0.07 0 0.07 C0.08 0 0.07 db v s = 2.7v, gain = 1, r l = 500 ? C0.11 C0.02 0.07 C0.13 C0.02 0.07 db v s = 2.7v, gain = 2, r l = 10k 5.94 6.01 6.08 5.93 6.01 6.08 db v s = 2.7v, gain = 4, r l = 10k 11.9 12.02 12.12 11.88 12.02 12.12 db v s = 2.7v, gain = 8, r l = 10k 17.8 18.0 18.15 17.75 18.0 18.15 db v s = 2.7v, gain = 8, r l = 500 ? 17.65 17.94 18.15 17.50 17.94 18.15 db v s = 2.7v, gain = 16, r l =10k 23.8 24.01 24.25 23.75 24.01 24.25 db v s = 2.7v, gain = 32, r l = 10k 29.7 30.0 30.2 29.65 30.0 30.2 db v s = 2.7v, gain = 64, r l = 10k 35.4 35.8 36.2 35.15 35.8 36.2 db v s = 2.7v, gain = 64, r l = 500 ? 34.15 35.3 36.0 33.40 35.3 36.0 db v s = 5v, gain = 1, r l = 10k C0.08 0 0.08 C0.09 0 0.08 db v s = 5v, gain = 1, r l = 500 ? C0.1 C0.01 0.08 C0.12 C0.01 0.08 db v s = 5v, gain = 2, r l = 10k 5.95 6.02 6.09 5.94 6.02 6.09 db v s = 5v, gain = 4, r l = 10k 11.85 12.02 12.15 11.83 12.02 12.15 db v s = 5v, gain = 8, r l = 10k 17.85 18.01 18.15 17.83 18.01 18.15 db v s = 5v, gain = 8, r l = 500 ? 17.65 17.96 18.15 17.50 17.96 18.15 db v s = 5v, gain = 16, r l = 10k 23.85 24.02 24.15 23.80 24.02 24.15 db v s = 5v, gain = 32, r l = 10k 29.70 30.02 30.2 29.65 30.02 30.2 db v s = 5v, gain = 64, r l = 10k 35.5 35.9 36.25 35.40 35.9 36.25 db v s = 5v, gain = 64, r l = 500 ? 34.6 35.6 36.0 33.8 35.6 36.0 db v s = 5v, gain = 1, r l = 10k C0.06 0.01 0.08 C0.07 0.01 0.08 db v s = 5v, gain = 1, r l = 500 ? C0.1 0 0.08 C0.11 0 0.08 db v s = 5v, gain = 2, r l = 10k 5.95 6.02 6.09 5.94 6.02 6.09 db v s = 5v, gain = 4, r l = 10k 11.9 12.03 12.15 11.88 12.03 12.15 db v s = 5v, gain = 8, r l = 10k 17.85 18.02 18.15 17.83 18.02 18.15 db v s = 5v, gain = 8, r l = 500 ? 17.80 17.99 18.15 17.73 17.99 18.15 db v s = 5v, gain = 16, r l = 10k 23.85 24.03 24.15 23.82 24.03 24.15 db v s = 5v, gain = 32, r l = 10k 29.85 30.0 30.2 29.8 30.0 30.20 db v s = 5v, gain = 64, r l = 10k 35.65 36.0 36.20 35.55 36.0 36.20 db v s = 5v, gain = 64, r l = 500 ? 35.15 35.8 36.10 34.45 35.8 36.10 db
ltc6912 9 6912fa the denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1, r l = 10k to midsupply point, unless otherwise noted. electrical characteristics c, i grades h grade parameter conditions min typ max min typ max units specifications for the ltc6912-2 only channel-to-channel v s = 2.7v, gain = 1, r l = 10k C0.1 0.02 0.1 C0.1 0.02 0.1 db voltage gain match v s = 2.7v, gain = 1, r l = 500 ? C0.1 0.02 0.1 C0.1 0.02 0.1 db (note 6) v s = 2.7v, gain = 2, r l = 10k C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 2.7v, gain = 4, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 2.7v, gain = 8, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 2.7v, gain = 8, r l = 500 ? C0.15 0.02 0.15 C0.2 0.02 0.2 db v s = 2.7v, gain = 16, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 2.7v, gain = 32, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 2.7v, gain = 64, r l = 10k C0.2 0.02 0.2 C0.2 0.02 0.2 db v s = 2.7v, gain = 64, r l = 500 ? C0.7 0.02 0.7 C1.0 0.02 1.0 db v s = 5v, gain = 1, r l = 10k C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 5v, gain = 1, r l = 500 ? C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 5v, gain = 2, r l = 10k C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 5v, gain = 4, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 8, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 8, r l = 500 ? C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 16, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 32, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 64, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 64, r l = 500 ? C0.6 0.02 0.6 C0.8 0.02 0.8 db v s = 5v, gain = 1, r l = 10k C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 5v, gain = 1, r l = 500 ? C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 5v, gain = 2, r l = 10k C0.1 0.02 0.1 C0.1 0.02 0.1 db v s = 5v, gain = 4, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 8, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 8, r l = 500 ? C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 16, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 32, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 64, r l = 10k C0.15 0.02 0.15 C0.15 0.02 0.15 db v s = 5v, gain = 64, r l = 500 ? C0.4 0.02 0.4 C0.6 0.02 0.6 db gain temperature coefficient v s = 5v, gain = 1, r l = open 2 2 ppm/ c (note 6) v s = 5v, gain = 2, r l = open C4 C4 ppm/ c v s = 5v, gain = 4, r l = open C10 C10 ppm/ c v s = 5v, gain = 8, r l = open C24 C24 ppm/ c v s = 5v, gain = 16, r l = open C30 C30 ppm/ c v s = 5v, gain = 32, r l = open C40 C40 ppm/ c v s = 5v, gain = 64, r l = open C120 C120 ppm/ c channel-to-channel gain v s = 5v, gain = 1, r l = open 0 0 ppm/ c temperature coefficient match v s = 5v, gain = 2, r l = open C0.5 C0.5 ppm/ c (note 6) v s = 5v, gain = 4, r l = open 0 0 ppm/ c v s = 5v, gain = 8, r l = open 0 0 ppm/ c v s = 5v, gain = 16, r l = open C1 C1 ppm/ c v s = 5v, gain = 32, r l = open C4 C4 ppm/ c v s = 5v, gain = 64, r l = open C4 C4 ppm/ c channel-to-channel isolation f = 200khz, (note 7) v s = 5v, gain = 1, r l = 10k 117 117 db v s = 5v, gain = 8, r l = 10k 110 110 db v s = 5v, gain = 64, r l = 10k 92 92 db offset voltage magnitude gain = 1 0.125 2 0.125 3.5 mv (internal op-amp, note 8)
ltc6912 10 6912fa electrical characteristics the denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1, r l = 10k to midsupply point, unless otherwise noted. c, i grades h grade parameter conditions min typ max min typ max units specifications for the ltc6912-2 only offset voltage magnitude gain = 1 0.25 3.5 0.25 6.5 mv referred to ina or inb pins gain = 8 0.14 2 0.14 4 mv (note 8) input offset voltage drift, 6 10 v/ c internal op amp dc input resistance at dc v ina or v inb = 0v ina or inb pins (note 9) gain = 0 >10 >10 m ? state = 8, software shutdown >10 >10 m ? gain = 1 10 10 k ? gain = 2 55k ? gain = 4 2.5 2.5 k ? gain > 4 1.25 1.25 k ? dc input resistance drift at gain = 1 85 95 ppm/ c ina or inb pins (note 9) gain = 2 90 100 ppm/ c gain = 4 95 105 ppm/ c gain = 8 120 130 ppm/ c gain = 16 130 140 ppm/ c gain = 32 140 150 ppm/ c gain = 64 170 180 ppm/ c dc input resistance match gain = 1 10 10 ? r ina -r inb gain = 2 55 ? gain = 4 55 ? gain > 4 55 ? dc small signal output resistance dc v ina or v inb = 0v at out a or out b pins gain = 0 0.4 0.4 ? gain = 1 0.7 0.7 ? gain = 2 1.0 1.0 ? gain = 4 1.9 1.9 ? gain = 8 3.4 3.4 ? gain = 16 6.4 6.4 ? gain = 32 15 15 ? gain = 64 30 30 ? state = 8, software shutdown >1 >1 m ? gain bandwidth product gain = 64 17 30 50 15 30 50 mhz wideband noise f = 1khz to 200khz (referred to input) gain = 0 (output noise only) 8.1 8.1 v rms gain = 1 13.8 13.8 v rms gain = 2 9.6 9.6 v rms gain = 4 7.5 7.5 v rms gain = 8 6.4 6.4 v rms gain = 16 6.0 6.0 v rms gain = 32 5.8 5.8 v rms gain = 64 5.6 5.6 v rms
ltc6912 11 6912fa electrical characteristics the denotes the specifications that apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v s = 5v, agnd = 2.5v, gain = 1, r l = 10k to midsupply point, unless otherwise noted. u u serial i terface specificatio s c, i grades h grade parameter conditions min typ max min typ max units specifications for the ltc6912-2 only voltage noise density f = 50khz (referred to input) gain = 1 31.1 31.1 nv/ hz gain = 2 22.8 22.8 nv/ hz gain = 4 17 17 nv/ hz gain = 8 14.6 14.6 nv/ hz gain = 16 13.2 13.2 nv/ hz gain = 32 12.9 12.9 nv/ hz gain = 64 12.6 12.6 nv/ hz total harmonic distortion gain = 8, f in = 10khz, v out = 1v rms C84 C84 db 0.006 0.006 % gain = 8, f in = 100khz, v out = 1v rms C82 C82 db 0.008 0.008 % symbol parameter conditions min typ max units digital i/o logic levels, all digital i/o voltage referenced to dgnd v ih digital input high voltage 2v v il digital input low voltage 0.8 v v oh digital output high voltage sourcing 500 a v + C 0.3 v v ol digital output low voltage sinking 500 a 0.3 v serial interface timing, v + = 2.7v ~ 4.5v, v = 0v (note 10) t 1 d in valid to clk setup 60 ns t 2 d in valid to clk hold 0ns t 3 clk low 100 ns t 4 clk high 100 ns t 5 cs/ld pulse width 60 ns t 6 lsb clk to cs/ld 60 ns t 7 cs/ld low to clk 30 ns t 8 d out output delay c l = 15pf 125 ns t 9 clk low to cs/ld low 0ns serial interface timing, v + = 4.5v ~ 5.5v, v = 0v (note 10) t 1 d in valid to clk setup 30 ns t 2 d in valid to clk hold 0ns t 3 clk low 50 ns t 4 clk high 50 ns t 5 cs/ld pulse width 40 ns t 6 lsb clk to cs/ld 40 ns t 7 cs/ld low to clk 20 ns t 8 d out output delay c l = 15pf 85 ns t 9 clk low to cs/ld low 0ns
ltc6912 12 6912fa note 1: absolute maximum ratings are those values beyond which the life of the device may be impaired. note 2: the ltc6912-1c and ltc6912-1i are guaranteed functional over the operating temperature range of C40 c to 85 c. the ltc6912-1h is guaranteed functional over the operating temperature range of C40 c to 125 c. note 3: the ltc6912-1c is guaranteed to meet specified performance from 0 c to 70 c. the ltc6912-1c is designed, characterized and expected to meet specified performance from C 40 c to 85 c but is not tested or qa sampled at these temperatures. the ltc6912-1i is guaranteed to meet specified performance from C40 c to 85 c. the ltc6912-1h is guaranteed to meet specified performance from C40 c to 125 c. note 4: output voltage swings are measured as differences between the output and the respective supply rail. note 5: extended operation with output shorted may cause junction temperature to exceed the 150 c limit for gn package and 125 c for a dfn package is not recommended. note 6: gain is measured with a large signal dc test using an output excursion between approximately 30% and 70% of supply voltage. note 7: channel-to-channel isolation is measured by applying a 200khz input signal to one channel so that its output varies 1v rms , and measuring the output voltage rms of the other channel relative to agnd with its input tied to agnd. isolation is calculated: isolation b = 20 ? log 10 (v outa /v outb ) or isolation a = 20 ? log 10 (v outb /v outa ) high channel-to-channel isolation is strongly dependent on proper circuit layout. see applications information. note 8: offset voltage referred to the ina or inb input is (1 + 1/|gain|) times the offset voltage of the internal op amp, where gain is the nominal gain magnitude. the typical offset voltage values are for 25 c only. see applications information. note 9: input resistance can vary by approximately 30% part-to-part at a given gain setting. note 10: guaranteed by design, not subject to test. note 11: states 13, 14 and 15 (binary 11xx) are not used. programming a channel to states 8 or higher will configure that particular channel into a low power shutdown state. in addition, programming a channel into state 15 (binary 1111) will cause that particular channel to draw up to 20ma of supply current and is not recommended. u u serial i terface specificatio s symbol parameter conditions min typ max units serial interface timing, dual 4.5v ~ 5.5v supplies (note 10) t 1 d in valid to clk setup 30 ns t 2 d in valid to clk hold 0ns t 3 clk high 50 ns t 4 clk low 50 ns t 5 cs/ld pulse width 40 ns t 6 lsb clk to cs/ld 40 ns t 7 cs/ld low to clk 20 ns t 8 d out output delay c l = 15pf 85 ns t 9 clk low to cs/ld low 0ns d3 d2 d31 d0 d3 d7 ? ? ? d4 d3 d4 d2 d31 d0 d3 d7 ? ? ? d4 t 5 t 8 t 9 t 7 t 6 t 1 t 2 t 4 t 3 6912 td previous byte current byte clk d in cs/ld d out
ltc6912 13 6912fa frequency (khz) gain (db) 50 40 30 20 10 0 C10 1 100 1000 10000 6912 g01 10 v s = 5v v in = 10mv rms gain of 100 gain of 50 gain of 20 gain of 10 gain of 1 gain of 5 gain of 2 frequency (hz) channel-to-channel gain match (db) 0.10 0.05 0 C0.05 C0.10 C0.15 C0.20 1 100 1000 10000 6912 g02 10 v s = 5v v in = 10mv rms gain of 100 gain of 10 gain of 1 gain (v/v) 1 0.1 C3db frequency (mhz) 1 6 10 100 6912 g03 v in = 10mv rms v s = 5v v s = 2.7v frequency (khz) 100 channel-to-channel isolation (db) 125 120 115 110 105 100 95 90 85 80 1000 6912 g04 gain of 100 gain of 10 gain of 1 frequency (khz) rejection (db) 90 80 70 60 50 40 30 20 10 0 1 100 1000 10000 6912 g05 6912 g06 10 v s = 5v v out = 1v rms v s = 5v gain = 1 +supply Csupply frequency (khz) 0 thd-amplitude below fundamental (db) C30 C40 C50 C60 C70 C80 C90 50 100 150 200 6912 g08 6912 g09 6912 g07 frequency (khz) 0 thd-amplitude below fundamental (db) 150 50 100 200 C50 C55 C60 C65 C70 C75 C80 C85 C90 gain of 100 gain of 10 gain of 1 r l = 500 ? v s = 2.5v v out = 1v rms (2.83)v p-p gain of 100 gain of 10 gain of 1 r l = 10k v s = 2.5v v out = 1v rms (2.83)v p-p input voltage (v p-p ) thd plus noise (db) C30 C40 C50 C60 C70 C80 C90 C100 0.001 0.1 1 10 0.01 v s = 5v r l = 10k f in = 1khz bw = 22khz gain of 100 gain of 10 gain of 1 frequency (khz) 1 1 voltage noise density (nv/hz) 10 100 10 100 v s = 2.5v t a = 25c input referred gain of 100 gain of 10 gain of 1 typical perfor a ce characteristics uw ltc6912-1 frequency response ltc6912-1 channel gain matching vs frequency ltc6912-1 e3db bandwidth vs gain setting ltc6912-1 channel isolation vs frequency ltc6912-1 power supply rejection vs frequency ltc6912-1 noise density vs frequency ltc6912-1 distortion vs frequency with light loading ltc6912-1 distortion vs frequency with heavy loading ltc6912-1 thd plus noise vs input voltage
ltc6912 14 6912fa frequency (khz) gain (db) 40 30 20 10 0 C10 1 100 1000 10000 6912 g14a 10 gain of 64 gain of 32 gain of 16 gain of 8 gain of 4 gain of 2 gain of 1 v s = 5v v in = 10mv rm s frequency (khz) 1 channel-to-channel gain match (db) 100 10000 0.100 0.075 0.050 0.025 0 C0.025 C0.050 C0.075 C0.100 6912 g15 10 1000 v s = 5v v in = 10mv rm s r l = 10k ? gain of 64 gain = 64 gain = 8 gain = 1 gain of 8 gain of 1 gain (v/v) 1 0.4 C3db frequency (mhz) 1.0 0.8 0.6 8.0 6.0 4.0 2.0 10 100 6912 g16 v in = 10mv rm s v s = 5v v s = 2.7v frequency (khz) 100 channel-to-channel i s olation (db) 125 120 115 110 105 100 95 90 85 80 1000 6912 g17 v s = 5v v out = 1v rm s total s upply current (a) temperature (c) C50 25 75 C25 0 50 100 125 6912 g10 10 1 0.1 hardware s hutdown (gn-16 only) v s = 5v v s = 5v v s = 3v v s = 2.7v temperature (c) C50 total s upply current (a) 700 600 500 400 300 200 100 25 75 6912 g11 C25 0 50 100 125 temperature (c) C50 25 75 6912 g14 C25 0 50 100 125 temperature (c) C50 25 75 6912 g13 C25 0 50 100 125 temperature (c) C50 total s upply current (ma) 100 6912 g12 050 5.00 4.75 4.50 4.25 4.00 3.75 3.50 3.25 3.00 C25 25 75 125 0.10 0.05 0 C0.05 C0.10 C0.15 C0.20 C0.25 gain change (db) 0.5 0 C0.5 C1.0 C1.5 gain change (db) both amplifier s in s oftware s hutdown r l = 10k v s = 5v v s = 5v v s = 2.7v both amplifier s programmed to gain = 1 r l = 10k v s = 5v v s = 5v v s = 2.7v gain of 1 gain of 10 gain of 100 v s = 5v r l = 10k gain of 1 gain of 10 gain of 100 v s = 5v r l = 500 ? ltc6912-1 hardware shutdown total supply current vs temperature ltc6912-1 software shutdown total supply current vs temperature ltc6912-1 total supply current vs temperature (both amplifiers active) ltc6912-1 gain shift vs temperature (light load) ltc6912-2 frequency response ltc6912-2 channel gain matching vs frequency ltc6912-2 ?db bandwidth vs gain setting ltc6912-2 channel isolation vs frequency typical perfor a ce characteristics uw ltc6912-1 gain shift vs temperature (heavy load)
ltc6912 15 6912fa frequency (khz) 1 rejection (db) 100 10000 90 80 70 60 50 40 30 20 10 0 6912 g18 10 1000 frequency (khz) 1 1 voltage noi s e den s ity ( n v/hz) 10 100 10 100 6912 g19 frequency (khz) 0 thd (amplitude below fundamental) (db) 150 6912 g20 50 100 200 C50 C55 C60 C65 C70 C75 C80 C85 C90 frequency (khz) 0 thd (amplitude below fundamental) (db) C30 C40 C50 C60 C70 C80 C90 C30 C40 C50 C60 C70 C80 C90 C100 50 100 150 200 6912 g21 input voltage (v p-p ) thd + noi s e (db) 0.001 0.1 1 10 6912 g22 0.01 temperature (c) C50 800 700 600 500 400 300 200 100 25 75 6912 g23 C25 0 50 100 125 temperature (c) C50 25 75 C25 0 50 100 125 total s upply current (a) temperature (c) C50 total s upply current (ma) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 25 75 6912 g24 C25 0 50 100 125 gain change (db) total s upply current (a) 6912 g25 temperature (c) C50 25 75 C25 0 50 100 125 6912 g22a 0.100 0.075 0.050 0.025 0 C0.025 C0.050 C0.075 C0.100 C0.125 C0.150 C0.175 C0.200 + s upply C s upply v s = 5v gain = 1 v s = 5v r l = 10k gain = 1 gain = 8 gain = 64 gain = 1 gain = 8 gain = 64 gain = 1 gain = 8 gain = 64 gain = 1 gain = 8 gain = 64 gain = 1 gain = 8 gain = 64 v s = 2.5v t a = 25c input referred v s = 5v r l = 10k f in = 1khz v s = 2.5v v out = 1v rm s (2.83v p-p ) v s = 2.5v v out = 1v rm s (2.83v p-p ) v s = 5v v s = 5v v s = 2.7v both amplifier s programmed to s tate = 8 r l = 10k v s = 5v v s = 5v v s = 2.7v both amplifier s active : gain = 1 r l = 10k 10 1 0.1 hardware s hutdown (gn-16 only) v s = 5v v s = 5v v s = 3v v s = 2.7v ltc6912-2 power supply rejection vs frequency ltc6912-2 noise density vs frequency ltc6912-2 distortion vs frequency with light loading (r l = 10k) ltc6912-2 distortion vs frequency with heavy loading (r l = 500 ? ) ltc6912-2 thd + noise vs input voltage ltc6912-2 software shutdown total supply current vs temperature ltc6912-2 total supply current vs temperature (both amplifiers active) ltc6912-2 gain shift vs temperature (light load) typical perfor a ce characteristics uw ltc6912-2 hardware shutdown total supply current vs temperature
ltc6912 16 6912fa ina, inb: analog inputs. the input signal to the a channel amplifier of the ltc6912-x is the voltage difference be- tween the ina pin and agnd pin. likewise, the input signal to the b channel amplifier of the ltc6912-x is the voltage difference between the inb pin and agnd pin. the ina (or inb) pin connects internally to a digitally controlled resis- tance whose other end is a current summing point at the same potential as the agnd pin (figure 1). at unity gain, the value of this input resistance is approximately 10k ? and the ina (or inb) pin voltage range is rail-to-rail (v + to v C ). at gain settings above unity, the input resistance falls. the linear input range at ina and inb also falls inversely proportional to the programmed gain. tables 1 and 2 summarize this behavior. the higher gains are designed to boost lower level signals with good noise performance. in the zero gain state (state = 0), or in software shutdown (state = 8) analog switches disconnect the ina or inb pin internally and this pin presents a very high input resis- tance. in the zero gain state (state = 0), the input may vary from rail to rail but the output is insensitive to it and is forced to the agnd potential. circuitry driving the ina and inb pins must consider the ltc6912-xs input resis- tance, its process variance, and the variation of this resistance from gain setting to gain setting. signal sources with significant output resistance may introduce a gain error as the sources output resistance and the ltc6912- xs input resistance forms a voltage divider. this is espe- cially true at higher gain settings where the input resis- tance is the lowest. uu u pi fu ctio s figure 1. gn-16 block diagram + C + C mos input op amp mos input op amp v + v + v C shdn cs/ld data clk 6912 bd lower nibble upper nibble 8-bit latch 8-bit shift-register input r array feedback r array input r array feedback r array channel a channel b q0 q1 q2 q3 q4 q5 q6 q7 5 3 1 16 15 13 14 12 10 11 6 7 8 9 2 4 nc ina agnd v C out a out b nc v + nc dgnd d out inb 100k 100k in single supply voltage applications, the ltc6912-xs dc ground reference for both input and output is agnd, not v C. with increasing gains, the ltc6912-xs input voltage range for an unclipped output is no longer rail-to-rail but diminishes inversely to gain, centered about the agnd potential. typical perfor a ce characteristics uw ltc6912-2 gain shift vs temperature (heavy load) temperature (c) C50 25 75 C25 0 50 100 125 gain change (db) 0.25 0 C0.25 C0.50 C0.75 C1.00 6912 g26 v s = 5v r l = 500 gain = 1 gain = 8 gain = 64
ltc6912 17 6912fa agnd: analog ground. the agnd pin is at the midpoint of an internal resistive voltage divider, developing a potential halfway between the v + and v C pins. in normal operation, the agnd pin has an equivalent input resistance of nomi- nally 50k (figure 1). in order to reduce the quiescent supply current in hardware shutdown (shdn pin pulled to v + , gn-16 only), the equivalent series resistance of this pin significantly increases (to a value on the order of 800k ? with 5v supplies, but is highly supply voltage, temperature, and process dependent). agnd is the noninverting input to both the internal channel a and channel b amplifiers. this makes agnd the ground refer- ence voltage for the ina, inb, outa, and outb pins. recommended analog ground plane connection depends on how power is applied to the ltc6912-x (see figures 2, 3, and 4). single power supply applications typically use v C for the system signal ground. the analog ground plane in single-supply applications should therefore tie to v C , and the agnd pin should be bypassed to this ground plane by a high quality capacitor of at least 0.1 f (figure 2). the agnd pin provides an internal analog reference voltage at half the v + supply voltage. dual supply applications with symmetrical supplies (such as 5v) have a natural system ground plane potential of zero volts, in which the agnd pin can be directly tied to, making the zero volt ground plane the input and output reference voltage for the ltc6912-x (figure 3). finally, if dual asymmetrical power supplies are used, the supply ground is still the natural ground plane voltage. to maximize signal swing capability with an asymmetrical supply, however, it is often desirable to refer the ltc6912-xs analog input and output to a voltage equidistant from the two supply rails v + and v C . the agnd pin will provide such a potential when open-circuited and bypassed with a capacitor (figure 4). in noise sensitive applications where agnd does not tie directly to a ground plane, as in figures 2 and 4, it is important to ac-bypass the agnd pin. otherwise channel to channel isolation is degraded, and wideband noise will enter the signal path from the thermal noise of the internal voltage divider resistors which present a thvenin equivalent resistance of approximately 50k ? . this noise can reduce snr by at least 15db at high gain settings. an external capacitor from agnd to the ground plane, whose impedance is well below 50k ? at frequencies of interest, will filter and suppress this noise. a 0.1 f high quality capacitor is effective for frequencies down to 1khz. larger capacitors will extend this suppression to lower frequencies. this issue does not arise in dual supply applications because the agnd pin ties directly to ground. in applications requiring an analog ground reference other than half the total supply voltage, the user can override the built-in analog ground reference by tying the agnd pin to a reference voltage with the agnd voltage range specified in the electrical characteristics table. the agnd pin will load the external reference with approximately 50k ? returned to the half-supply potential. agnd should still be capaci- tively bypassed to a ground plane as noted above. do not connect the agnd pin to the v C pin. figure 2. single supply ground plane connection 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc6912-x serial interface 0.1 f v + digital ground plane analog ground plane single-point system gnd 0.1 f v + 2 reference 6912 f02 uu u pi fu ctio s figure 3. symmetrical dual supply ground plane connection 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc6912-x serial interface 0.1 f 0.1 f v + v C digital ground plane analog ground plane 6912 f03 single-point system gnd
ltc6912 18 6912fa shdn (gn-16 only): cmos compatible logic hardware shutdown input. the ltc6912-x has two shutdown modes. one is a software shutdown state which can be software programmed into either channel a, channel b, or both. the software shutdown, when programmed to a particular channel (state = 8), will disable that channels amplifier and tri-state open its analog input and analog output. the serial interface, however is still active. a hardware shut- down occurs when the shdn pin is pulled to the positive rail. in this condition, both amplifiers and serial interface are disabled. the shdn pin is allowed to swing from v C to 10.5v above v C , regardless of v + so long as the logic levels meet the minimum requirements specified in the electrical characteristics table. the shdn pin is a high impedance cmos logic input, but has a small pull-down current source (<10 a) which will force shdn low if the logic input is externally floated. on initial power up (with shdn open), or coming out of the hardware shutdown mode (pulling shdn to v C ), both amplifiers are reset into the power-on reset state (software shutdown mode, state = 8) for both channels. cs/ld: ttl/cmos compatible logic input. when this pin is asserted low, the clk pin is enabled, and the 8-bit shift register serially shifts the shift register contents and whatever data is present on the d in pin into the shift register on the rising edge of clk. on the rising edge of cs/ld, the contents of the shift register data are loaded into the eight bit latch which configures the gain state of both channel a and channel b amplifiers. a logic high on cs/ld inhibits the clk signal internally to the ic. d in : ttl/cmos compatible logic serial data input. the serial interface is synchronously loaded msb first via d in on the rising edge of clk with cs/ld asserted low. clk: ttl/cmos compatible logic input. with cs/ld asserted low, the clock synchronizes the loading of the serial shift register on its rising and falling edges. data is shifted in at d in on the rising edge of clk and is shifted out on d out on the falling edge of clk. d out : ttl/cmos compatible logic output. the msb of the shift register contents is shifted out at d out on the falling edge of clk. the output at d out swings between v + and dgnd, and is rated to drive approximately 15pf. dgnd: digital ground: the dgnd pin defines the potential from which logic levels v ih and v il for the 3-wire serial digital interface are referenced. the recommended con- nection of dgnd depends on how power is applied to the ltc6912 (see figures 2, 3, and 4). (caveat: under no conditions is dgnd to exceed either supply pins v + and v C , which could result in damage to the ic if not current limited.) single power supply applications typically use v C for the system signal ground. the preferred connection for dgnd is therefore v C (see figure 2). dual supply applications with symmetrical supplies (such as 5v) have a natural system ground potential of zero volts, in which the dgnd pin can be tied to, making the zero volt ground plane the logic reference (figure 3). finally, if dual asymmetrical power supplies are used, the system ground is still the natural ground plane voltage. v , v + : power supply pins. the v + and v C pins should be bypassed with 0.1 f capacitors to an adequate analog ground plane using the shortest possible wiring. electri- cally clean supplies and a low impedance ground are important for the high dynamic range available from the ltc6912 (see further details under the agnd pin descrip- tion). low noise linear power supplies are recommended. switching power supplies require special care to prevent switching noise coupling into the signal path, reducing dynamic range. uu u pi fu ctio s figure 4. asymmetrical dual supply ground plane connection 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc6912-x serial interface 0.1 f 0.1 f v + v C digital ground plane analog ground plane 0.1 f v + + v C 2 reference 6912 f04 single-point system gnd
ltc6912 19 6912fa uu u pi fu ctio s applicatio s i for atio wu u u functional description the ltc6912-x is a small outline, wideband, inverting two-channel amplifier with voltage gains that are indepen- dently programmable. each delivers a choice of eight voltage gains, configurable through a 3-wire serial digital interface, which accepts ttl or cmos logic levels (see figure 5). tables 1 and 2 list the nominal gains for the ltc6912-1 and ltc6912-2 respectively. gain control within the amplifier occurs by switching resistors from a matched array in or out of a closed-loop op amp circuit using mos analog switches (figure 1). the bandwidths of the individual amplifiers depend on gain setting. the typical performance characteristics section shows mea- sured frequency responses. description of the 3-wire spi interface gain control of each amplifier is independently program- mable using the 3-wire spi interface (see figure 5). logic levels for the ltc6912 3-wire serial interface are ttl/ cmos compatible. when cs/ld is low, the serial data on d in is shifted into an 8-bit shift-register on the rising edge of the clock, with the msb transferred first. serial data on d out is shifted out on the clocks falling edge. a rising edge on cs/ld will latch the shift-registers contents into an 8- bit d-latch and disable the clock internally on the ic. the upper nibble of the d-latch (4 most significant bits), configure the gain for the b-channel amplifier. the lower nibble of the d-latch (4 least significant bits), configures the gain for the a-channel amplifier. tables 1 and 2 detail the nominal gains and respective gain codes. care must be taken to ensure clk is taken low before cs/ld is pulled low to avoid an extra internal clock pulse to the input of the 8-bit shift-register (see figure 5). d out is active in all states, therefore d out cannot be wire-ord to other spi outputs. an ltc6912 may be daisy-chained with other ltc6912s or other devices having serial interfaces by connecting the d out to the d in of the next chip while clk and cs/ld remain common to all chips in the daisy chain. the serial data is clocked to all the chips then the cs/ld signal is pulled high to update all of them simultaneously. figure 6 shows an example of two ltc6912s in a daisy chained spi figure 5. serial digital interface block diagram clk cs/ld shdn 6912 f05 lower nibble upper nibble 8-bit latch 8-bit shift-register channel a channel b q0 q1 q2 q3 q4 q5 q6 q7 d out lsb msb reset reset le d in out a, out b: analog output. these pins are the output of the a and b channel amplifiers respectively. each operational amplifier can swing rail-to-rail (v + to v C ) as specified in the electrical characteristics table. for best performance, loading the output as lightly as possible will minimize signal distortion and gain error. the electrical characteristics table shows performance at output cur- rents up to 10ma, and the current limits which occur when the output is shorted midsupply at 2.7v and 5v supplies. output current above 10ma is possible but current-limit- ing circuitry will begin to affect amplifier performance at approximately 20ma. long-term operation above 20ma output is not recommended. do not exceed maximum junction temperature of 150 c for a gn and 125 c for a dfn package. the output will drive capacitive loads up to 50pf. capacitances higher than 50pf should be isolated by a series resistor (10 ? or higher).
ltc6912 20 6912fa applicatio s i for atio wu uu figure 6. two ltc6912s (four pgas) in daisy chain configuration 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc6912-x 0.1 f 0.1 f v + v C digital ground plane analog ground plane 6912 f06 dgnd d out 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ltc6912-x 0.1 f 0.1 f v + v C dgnd d out cs/ld data clk p single-point system gnd d15 d11 d10 d9 d8 d7 d3 d2 d1 d0 clk d in cs/ld shdn cs/ld d in shdn cs/ld d in configuration. it is recommended the serial interface sig- nals should remain idle in between data transfers in order to minimize digital noise coupling into the analog path. power on reset on the initial application of power, the power on reset state of both amplifiers is low power software shutdown (state = 8) (see tables 1 and 2). in this state, both analog amplifiers are disabled and have their inputs and outputs opened. this will facilitate the application of using the device as a 2:1 analog mux, in that the amplifiers outputs may be wired-or together and the ltc6912 can alter- nately select between a and b channels. care must be taken if the outputs are wired-ord to ensure the software shutdown state (state = 8) is always programmed in one of the two channels. timing constraints settling time in the cmos gain-control logic is typically several nanoseconds and is faster than the analog signal path. when the amplifier gain changes, the limiting timing is analog. as with any programmable-gain amplifier, each gain change causes an output transient as the amplifiers output moves, with finite speed, toward a differently scaled version of the input signal. the ltc6912-x analog path settles with a characteristic time constant or time scale, , that is roughly the standard value for a first order band limited response: = 0.35/f C3db see the C3db bw vs gain setting graph in the typical performance characteristics section.
ltc6912 21 6912fa applicatio s i for atio wu uu offset voltage vs gain setting the electrical tables list dc offset (error), v os(oa) , at the inputs of the internal op amp (see figure 1). the electrical tables also show the resulting, gain dependent offset voltage referred to the ina, or inb pins, v os(in) . the two measures are related through the feedback/input resistor ratio, which equals the nominal gain-magnitude setting, |gain|: v os(in) = (1 + 1/|gain|) v os(oa) offset voltages at any gain setting can be inferred from this relationship. for example, an internal amplifier offset v os(oa) of 1mv will appear referred to the ina, inb pins as 2mv at a gain setting of 1, or 1.5mv at a gain setting of 2. at high gains, v os(in) approaches v os(oa) . (offset voltage is random and can have either polarity centered on 0v). the mos input circuitry of the internal op amp in figure 1 draws negligible input currents (less than 10 a), so only v os(oa) and the gain affect the overall amplifiers offset. ac-coupled operation adding capacitors in series with the ina and inb pins converts the ltc6912-x into a dual ac-coupled inverting amplifier, suppressing the input signals dc level (and also adding the additional benefit of reducing the offset voltage from the ltc6912-xs amplifier itself). no further compo- nents are required because the input of the ltc6912-x biases itself correctly when a series capacitor is added. the ina and inb analog input pins connect internally to a resistor whose nominal value varies between 10k ? and 1k ? depending on the version of ltc6912 used (see the rightmost column of tables 1 and 2). therefore, the low frequency cutoff will vary with capacitor and gain setting. if, for example, a low frequency corner of 1khz (or lower) on the ltc6912-1 is desired, use a series capacitor of 0.16 f or larger. 0.16 f has a reactance of 1k ? at 1khz, giving a 1khz lower C3db frequency for gain settings of 10v/v through 100v/v. if the ltc6912-1 is operated at lower gain settings with a 0.16 f capacitor, the higher input resistance will reduce the lower corner frequency down to 100hz at a gain setting of 1v/v. these frequencies scale inversely with the value of input capacitor used. note that operating the ltc6912 family in zero gain mode (digital state 0000) open circuits both the ina and inb pins and this demands some care if employed with a series ac coupling input capacitor. when the chip enters the zero gain mode, the opened ina or inb pin tends to sample and freeze the voltage across the capacitor to the value it held just before the zero gain state. this can place the ina or inb pin at or near the dc potential of a supply rail. (the ina or inb pin may also drift to a supply potential in this state due to small leakage currents.) to prevent driving the ina or inb pin outside the supply limit and potentially damaging the chip, avoid ac input signals in the zero gain state with an ac coupling capacitor. also, switching later to a non-zero gain value will cause a transient pulse at the output of the ltc6912-1 (with a time constant set by the capacitor value and the new ltc6912-1 input resistance value). this occurs because the ina and inb pins return to the agnd potential forcing transient current sourced by the amplifier output to charge the ac coupling capacitor to its proper dc blocking value. snr and dynamic range the term dynamic range is much used (and abused) with signal paths. signal-to-noise (snr) is an unambigu- ous comparison of signal and noise levels, measured in the same way and under the same operating conditions. in a variable gain amplifier, however, further characterization is useful because both noise and maximum signal level in the amplifier will vary with the gain setting, in general. in the ltc6912-x, maximum output signal is independent of gain (and is near the full power supply voltage, as detailed in the swing sections of the electrical characteristics table). the maximum input level falls with increasing gain, and the input-referred noise falls as well (listed also in the table). to summarize the useful signal range in such an amplifier, we define dynamic range (dr) as the ratio of maximum input (at unity gain) to minimum input-referred noise (at maximum gain). this dr has a physical interpre- tation as the range of signal levels that will experience an snr above unity v/v or 0db. at a 10v total power supply, dr in the ltc6912-x (gains 0v/v to 100v/v), the dr is typically 115db (the ratio of 9.9 v p-p , or 3.5v rms , maxi- mum input to the 6.3 v rms high gain input noise). the
ltc6912 22 6912fa snr from an amplifier is the ratio of input level to input- referred noise, and can be 108db with the ltc6912 family at unity gain. construction and instrumentation cautions electrically clean construction is important in applications seeking the full dynamic range of the ltc6912 family of dual amplifiers. it is absolutely critical to have agnd either ac bypassed or wired directly using the shortest possible wiring, to a low impedance ground return for best channel- to-channel isolation. short, direct wiring minimizes para- sitic capacitance and inductance. high quality supply bypass capacitors of 0.1 f near the chip provide good applicatio s i for atio wu uu decoupling from a clean, low inductance power source. but several centimeters of wire (i.e., a few h of induc- tance) from the power supplies, unless decoupled by substantial capacitance (>10 f) near the chip, can create a parasitic high-q lc resonant circuit in the hundreds of khz range in the chips supplies or ground reference. this may impair circuit performance at those frequencies. a compact, carefully laid out printed circuit board with a good ground plane makes a significant difference in mini- mizing distortion. finally, equipment to measure perfor- mance can itself introduce distortion or noise floors. checking for these limits with wired shorts from ina to outa and inb to outb in place of the chip is a prudent routine procedure. typical applicatio u low noise ac amplifier with programmable gain and bandwidth analog data acquisition can exploit band limiting as well as gain to suppress unwanted signals or noise. tailoring an analog front end to both the level and bandwidth of each source maximizes the resulting snr. figure 7 shows a block diagram for a low noise amplifier with gain and bandwidth independently programmable over a 100:1 range. channels a and b of the ltc6912-1 are used to independently control the gain and bandwidth respec- tively over a 100:1 range. the lt1884 dual op amp forms an integrating lowpass loop with capacitor c2 to set the programmable upper corner frequency. the lt1884 also supports rail-to-rail output swings over the total supply voltage range of 2.7v to 10.5v. ac coupling through capacitor c1 establishes a fixed low frequency corner of 1hz, which can be adjusted by changing c1. alternatively, shorting c1 makes the amplifier dc coupled. if dc gain is not needed, the ac coupling cap c1 serves to suppress several error sources: any shift in dc levels, low frequency noise, and dc offset voltages (not including the lt1884s low internal offset). figure 7. block diagram of an ac amplifier with programmable gain and bandwidth C + C + v in v out gaina gainb c1 10 f c2 1 f r1 15.8k r2 15.8k 1m r r 1/2 lt1884 1/2 lt1884 1/2 lt1884 ltc6912-1 channel a ltc6912-1 channel b gain control pga bandwidth control pga v out = gaina v in r2 r1 6912 f07 ina outa inb outb 1 2 r1c1 1 r2 gainb 2 ( ) c2 C3db bandwidth range is from to
ltc6912 23 6912fa de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695) 4.00 0.10 (2 sides) 3.00 0.10 (2 sides) 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 0.38 0.10 bottom viewexposed pad 1.70 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 0.25 0.05 3.30 0.10 (2 sides) 1 6 12 7 0.50 bsc pin 1 notch pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (ue12/de12) dfn 0603 0.25 0.05 3.30 0.05 (2 sides) recommended solder pad pitch and dimensions 1.70 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline u package descriptio gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 C .244 (5.817 C 6.198) .150 C .157** (3.810 C 3.988) 16 15 14 13 .189 C .196* (4.801 C 4.978) 12 11 10 9 .016 C .050 (0.406 C 1.270) .015 .004 (0.38 0.10) 45 0 C 8 typ .007 C .0098 (0.178 C 0.249) .0532 C .0688 (1.35 C 1.75) .008 C .012 (0.203 C 0.305) typ .004 C .0098 (0.102 C 0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 C .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc6912 24 6912fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2004 lt/lt 1005 rev a ? printed in usa related parts part number description comments lt1228 100mhz gain controlled transconductance amplifier differential input, continuous analog gain control lt1251/lt1256 40mhz video fader and gain controlled amplifier two input, one output, continuous analog gain control ltc1564 10khz to 150khz digitally controlled filter and pga continuous time, low noise 8th order filter and 4-bit pga ltc6910-1/-2/-3 digitally controlled programmable gain amplifier single programmable gain amplifier, 3-bit parallel digital inter face in sot-23 ltc6911-1/-2 dual digitally controlled programmable gain amplifier dual programmable gain amplifiers, 3-bit parallel digital inte rface in msop-10 ltc6915 zero drift instrumentation amp gains 0 - 4096v/v, 116db cmrr with digitally programmable gain u typical applicatio ina agnd inb 1 f 0.1 f channel a input channel b input v out (to adc) out a out b ltc6912-x v + v + v C shdn cs/ld data clk shdn cs/ld d in 5 6 7 8 10 9 dgnd d out 2 12 14 3 4 15 13 chb cha 3-wire spi interface 6912 ta02 mux operation: if the lower nibble (q3, q2, q1, q0) is (1, 0, 0, 0) then outa is in tri-state and the upper nibble (q7, q6, q5, q4) controls the active channel b. if the upper nibble is (1, 0, 0, 0) then outb is in tri-state and the lower nibble controls active channel a. a 2:1 pga mux

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Price & Availability of LTC6912CDE-2TR

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